Technological innovation_Changsha AMQ Intelligent Technology Co.. Ltd

Innovation

National high-tech enterprise focusing on high-end chip packaging

IndiumPk™

AMQ is proud to be the pioneering OSAT provider to adapt Indium as a core packaging material, leading a new chapter in electronic device reliability and performance.

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Packaging design and simulation

AMQ's design team possesses extensive design and simulation experience in the electronics market, covering mobile, network, computer, consumer, and automotive products.

This encompasses laminate, wire-bonded, flip-chip, and system-in-package designs, including single-mode, multi-mode, package-on-package (PoP), integrated passive devices (IPD), and advanced three-dimensional system-in-package (SiP) technologies.

Through close collaboration with clients, we strive to deliver optimal products in terms of performance, quality, lead time, and cost, assisting clients in determining the best packaging solutions for their products.

The design and simulation team works closely with clients, employing collaborative design to ensure that semiconductor packaging meets thermal and electrical performance requirements.

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Large and multi-chip specialty

AMQ stands as China’s industry leader in large-scale and multi-chip packaging innovation, being the first domestic OSAT provider to successfully create the largest chip package and to pioneer the “first four-chip integrated package” in China. These achievements firmly establish AMQ’s technical prowess and superiority in the field.

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Whitepapers

《Influence of surface roughness on interfacial reaction and shear strength ofindium thermal interface materials for FCBGA packaging》

As electronic devices continue to evolve toward higher power consumption, pure indium is gradually emerging as an ideal metal thermal interface material (TIM) for flip-chip ball-grid array (FCBGA) packaging products, driving strong market demand. However, ensuring the reliability of indium-based thermal interface materials (TIMs) during repeated high-temperature reflow (HTR) processes remains a significant challenge for FCBGA packaging. In this study, we focused on the assembly consisting of a cover plate, indium, and a BSM chip, examining the wettability between indium and various interfaces within a temperature range of 170–245°C. We also systematically analyzed the effects of different process conditions on interfacial reactions and shear strength. The results indicate that increasing the temperature and reducing the surface roughness of the coating can enhance the wettability of indium at different interfaces. In contrast, cover plates with a surface roughness of 0.4 < Ra < 0.6 better meet the requirements of FCBGA processing. Under low-temperature reflow (LTR) and repeated high-temperature reflow conditions, the primary fracture mode observed was ductile fracture.

01-30

2026

《Investigation on Thermal-Mechanical Reliability and Enhanced Fatigue Life of Indium Thermal Interface Materials for Large-Size Flip Chip Packaging》

With the growing demand for thermal management in large-size chips, indium—due to its inherent high thermal conductivity and excellent ductility—is considered an ideal thermal interface material (TIM). For large-size flip-chip packages, enhancing reliability, especially under temperature cycling conditions, remains a significant challenge. This study focuses on large-size flip-chip packaging and employs a combined approach of finite-element simulation and experiments to systematically analyze the creep behavior and morphological evolution of indium under temperature cycling. Based on this analysis, the strain-based Coffin–Manson model was used to predict the fatigue life of indium. To improve the reliability of the indium layer under temperature cycling, design-of-experiments (DOEs) were employed to simulate and analyze the effects of various structural parameters on fatigue life. The results show that the cumulative plastic strain is greatest near the chip edges, which correlates well with the crack locations observed in actual measurements. The fatigue life of the indium layer predicted by the Coffin–Manson model is in good agreement with the experimental results. Signal-to-noise ratio (SNR) analysis indicates that the thickness of the indium layer has the most significant impact on thermal fatigue life, while the adhesive thickness has the least influence. Compared to the original model, the optimized package structure exhibits a 135% improvement in fatigue life.

01-30

2026

《Investigation on Indium Thermal Interface Materials Fluxless Bonding Technology via In Situ Formed AgIn2 Coating》

Indium (In) is widely used as a solder-based thermal interface material (TIM1) in high-power central processing unit (CPU) chips, primarily because it enhances thermal performance. However, residual organic fluxes in indium solder can release gases during the solder ball reflow process, leading to a high void fraction—approximately 35%—in indium TIM1. This limitation restricts its application in advanced ball grid array (BGA) packaging. In this study, to achieve flux-free indium reflow and obtain indium TIM1 with a low void fraction, a thin silver (Ag) layer was electroplated onto the surface of thick indium TIM1, enabling in-situ formation of an AgIn₂ coating that effectively prevents indium oxidation. Consequently, no flux is required during the reflow process to remove the oxide layer from the solder. After one indium reflow and three solder ball reflows, scanning acoustic microscopy (SAM) confirmed the formation of joints with a low void fraction (4.2%). Moreover, the resulting joints exhibited improved thermal conductivity and mechanical performance—showing an enhancement of 11.4%. Additionally, a novel decomposition mechanism of the AgIn₂ coating during reflow was identified: During indium reflow, AgIn₂ decomposes into indium atoms and silver atoms. The silver atoms enhance the wettability of the solder and improve the shear strength of the joint.

01-30

2026

《Investigation on warpage characteristics for ultra- large MCM FCBGA package based on material-structure co-design and intelligent optimization》

The growing demand for computational power driven by artificial intelligence (AI) and high-performance computing (HPC) has spurred significant advances in multi-chip integration and large-scale packaging approaches. As a result, multi-chip module (MCM) packaging has emerged as a prominent technological solution. However, the mismatch in thermal expansion coefficients (CTE) between silicon chips and organic substrates can exacerbate warpage, leading to process and reliability issues such as solder bump bridging, non-wetting, and solder ball cracking. Consequently, warpage control has become a critical challenge for these types of products. This study proposes a warpage-control approach that integrates material-structure co-design with hybrid intelligent optimization. A simulation model of a 4-chip 102 mm × 102 mm flip-chip ball grid array (FCBGA) package, validated through shadow moiré experiments, achieves a prediction error of ≤7.4%. The warpage exhibits a non-uniform wave pattern influenced by chip layout; key factors affecting warpage include chip spacing, substrate thermal expansion coefficient, ring thermal expansion coefficient, ring foot width, and ring foot thickness. A customized response surface methodology (RSM) accurately captures the nonlinear coupling effects, while a hybrid NSGA-II and PSO algorithm optimizes warpage control. Full-parameter optimization reduces warpage by 33.5% (to 138.5 μm) at 30 °C and by 88.3% (to 28.6 μm) at 245 °C. When optimizing only the ring structure, the warpage improvement is even more pronounced: at 30 °C, warpage is reduced by 50.9% (to 102.2 μm), and at 245 °C, by 32.2% (to 166.4 μm). The proposed approach offers new insights and an effective strategy for warpage control in large-scale MCM packaging.

01-30

2026

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